The pulse domain (also known as the time domain) is becoming a more and more desirable domain for information encoding and/or transfer. In the analog domain signals are typically represented by both their amplitudes and shapes. In the digital domain, signals represent binary numbers and the intervals between the 1's and 0's of the digital information is typically regulated by a clock in the digital domain so such signals in the digital domain are synchronous with the clock. The digital domain has both advantages and disadvantages compared to the analog domain. The digital domain is resistant to amplitude excursions which hamper the analog domain, but a digital domain signal is typically just an approximation of a corresponding analog signal. Information can be lost when an analog signal is digitized.
In contrast, in the pulse domain information (data) is encoded by pulses and it is the interval between successive pulses (and not their amplitudes) which encodes the information (data) being conveyed by a pulse domain signal. So a pulse domain signal has certain advantages over signals in either the digital or analog domains.
However, there are instances when it is advantageous to transfer information from the pulse (or time) domain to the digital domain. See, for example, U.S. Pat. No. 9,154,172 issued Oct. 6, 2015. The present invention relates a Asynchronous-to-Synchronous Time-to-Digital Converter which facilitates such a transfer of information.
The prior art includes: X. Kong et al., “A Time-Encoding Machine Based High-Speed Analog-to-Digital Converter”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, No. 3, September 2012. See also FIG. 1. This prior art circuit utilizes a de-multiplexer (DeMUX), multiple pulse-to-voltage (P2V) converters, and multiple analog-to-digital converters (ADC). This circuit has the disadvantages of (i) a large implementation area and high power consumption due to this large number of the building blocks, and (ii) a proneness to process, voltage and temperature (PVT) variations of the contemporary semiconductor technology since the building blocks of P2V and ADC have to be implemented in analog circuits.
Asynchronous-to-synchronous converters which operate in solely in the digital domain are known, which prior art also includes: R. Sharma et al., “Asynchronous-to-Synchronous Converter”, U.S. Pat. No. 5,268,934, Dec. 7, 1993; R. Tyrrel, “Asynchronous-to-Synchronous Data Interface”, U.S. Pat. No. 4,586,189, Apr. 29, 1986; and G. Offord, “Low-Power Area-Efficient and Robust Asynchronous-to-Synchronous Interface”, U.S. Pat. No. 5,522,048, May 28, 1996. See also FIGS. 2-4 from these patents. This prior art relates to asynchronous-to-synchronous converters. The prior art shown in FIGS. 2 and 3 is mainly targeting at data transfer over a RS-232 communication channel, so both require the start and stop bits for the conversion process, which involves a significant communication overhead due to these extra bits. The prior art represented by FIG. 4 aims for an interface between a master chip and a target chip. However, it cannot guarantee not to generate duplicated data at the system/application level. Consequently, this prior art has a disadvantage of high risk of generating system/application malfunctions that are related to data duplications.
More importantly, the prior art represented by FIGS. 2-4 is not capable of converting information (date) from the pulse domain to the digital domain.